What is the SIMPLEST way for implementing the box "A" with the
following specification ?
The input is either connected to -5V or GND.
when input = -5V the output should be logic 1 (TTL or CMOS).
when input = GND the output should be logic 0 (TTL or CMOS).
The only available voltages that could be used inside A are
+5V and GND (not -5V).
__________
| |
| |
(inp. -5V/0V)—–> | A |——>(outp. TTL/CMOS 1/0)
| |
|_________|
Thanks a lot in advance
——————————–
m.k.iranp…@fys.uio.no wrote:
: What is the SIMPLEST way for implementing the box "A" with the
: following specification ?
: The input is either connected to -5V or GND.
: when input = -5V the output should be logic 1 (TTL or CMOS).
: when input = GND the output should be logic 0 (TTL or CMOS).
: The only available voltages that could be used inside A are
: +5V and GND (not -5V).
: __________
: | |
: | |
: (inp. -5V/0V)—–> | A |——>(outp. TTL/CMOS 1/0)
: | |
: |_________|
A simple comparitor is one way. You can even use a single supply
el-cheapo like one of the sections of an LM339 or LM393 (it is not
necessary to use a negative supply). Just bias the non-inverting input
at a handy voltage (say, 2.5 Volts, for example) using a pair of 10K
resistors (for example) hung from the +5 V supply to ground. Then hang
another 2 resistors in series from +5 V, to the input signal. Connect the
inverting input to the node between these resistors. The value of these
resistors is selected so the the input is not excessively loaded, and so
that when the input is -5 V, the (-) input of the comparitor is below
the voltage setpoint at the (+) input, and when the input voltage is 0
V, the voltage at the (-) input is above the voltage setpoint at the (+)
input. Don’t forget the comparitor’s output pullup resistor.
But you can get even more trivial than this. Use an ordinary digital
inverter (or a NAND gate, or a NOR gate that you have hanging around
unused) instead of a comparitor and connect the input to the above
resistor chain that hangs from the +5 V line to -5V/0V logic that you
are trying to convert. All you need here, then, is an inverter in the
logic family of your choice (the 74HC family is a nice choice) and 2
resistors.
Seems to me that one of the first things we covered in the very first
introductory course in digital logic I took years ago covered
interfacing between weird voltage levels and standard logic devices (or
vice versa). Odd that you haven’t run across it yet.
Bob.
- Hide quoted text — Show quoted text -
m.k.iranp…@fys.uio.no wrote:
> What is the SIMPLEST way for implementing the box "A" with the
> following specification ?
> The input is either connected to -5V or GND.
> when input = -5V the output should be logic 1 (TTL or CMOS).
> when input = GND the output should be logic 0 (TTL or CMOS).
> The only available voltages that could be used inside A are
> +5V and GND (not -5V).
> __________
> | |
> | |
> (inp. -5V/0V)—–> | A |——>(outp. TTL/CMOS 1/0)
> | |
> |_________|
> Thanks a lot in advance
Use a bipolar NPN with pullup resistor from the collector to +5 V, base
to 0 V, and a second resistor to the emitter. The other end of the
emitter resistor is the input and the collector is the output. When the
input (emitter resistor) is at 0V the transistor is in cutoff and the
output (collector) is pulled high. When the input is at -5V the
transistor is saturated and the output is driven low.
I used such a circuit years ago to convert RS-232 logic levels (<-3,
>+3) to TTL logic levels.
Matt
—
maboy…@geocities.com
http://www.geocities.com/CapeCanaveral/3041
- Hide quoted text — Show quoted text -
m.k.iranp…@fys.uio.no wrote:
> What is the SIMPLEST way for implementing the box "A" with the
> following specification ?
> The input is either connected to -5V or GND.
> when input = -5V the output should be logic 1 (TTL or CMOS).
> when input = GND the output should be logic 0 (TTL or CMOS).
> The only available voltages that could be used inside A are
> +5V and GND (not -5V).
> __________
> | |
> | |
> (inp. -5V/0V)—–> | A |——>(outp. TTL/CMOS 1/0)
> | |
> |_________|
> Thanks a lot in advance
> ——————————–
Just use a JFET with a pull up resistor.
- Hide quoted text — Show quoted text -
Jim Onderko wrote:
> m.k.iranp…@fys.uio.no wrote:
> > What is the SIMPLEST way for implementing the box "A" with the
> > following specification ?
> > The input is either connected to -5V or GND.
> > when input = -5V the output should be logic 1 (TTL or CMOS).
> > when input = GND the output should be logic 0 (TTL or CMOS).
> > The only available voltages that could be used inside A are
> > +5V and GND (not -5V).
> > __________
> > | |
> > | |
> > (inp. -5V/0V)—–> | A |——>(outp. TTL/CMOS 1/0)
> > | |
> > |_________|
> > Thanks a lot in advance
> > ——————————–
> Just use a JFET with a pull up resistor.
…
The most universal solution would be to use an optoisolator. That way
you simply drive a LED (inside the isolator) with whatever voltage you
need,
set the current thru the LED by picking appropriate series resistors,
and any other needed signal conditioning stuff like:
– adding a reverse diode if the input is AC (Protect LED from reverse
V)
— Using a series Zener diode to make it a ‘voltage is above X’ sensor
— Adding some RC filtering for noise / time response
Some optoisolators (??The 4N138?) have VERY low current requirements
(less than 1 mA) and can sense lots of interesting stuff, like telephone
ring, telephone off-hook, audio from the Baby Monitor etc.
Regards, Terry King …In The Woods In Vermont
Equipment Engineer
Little Castle Studio
Box 633 2173 Shelburne Road
Shelburne, Vermont 05482
tk…@together.net
<huge snip>
>But you can get even more trivial than this. Use an ordinary digital
>inverter (or a NAND gate, or a NOR gate that you have hanging around
>unused) instead of a comparitor and connect the input to the above
>resistor chain that hangs from the +5 V line to -5V/0V logic that you
>are trying to convert. All you need here, then, is an inverter in the
>logic family of your choice (the 74HC family is a nice choice) and 2
>resistors.
<snarky comment snipped>
Just make sure that ground bounce or whatever isn’t going to take the
input to your inverter/NAND gate/NOR gate below Vss-0.6V ( -0.3V is
safer).
If you do, you draw current from the substrate of the package, and this
can have unpredictable effects on any other other gate in the
package – one of the other outputs may go high or low while you are
drawing current.
This is why "ground bounce" is such a bad thing in fast TTL systems.Can
cause very odd behaviour in flip-flops.
Protecting against this means using three resistors and a catching diode
to Vss; the catching diode should see -0.6V or lower when the logic
input is at 0V.
Bill Sloman (slo…@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
m.k.iranp…@fys.uio.no wrote:
> What is the SIMPLEST way for implementing the box "A" with the
> following specification ?
> The input is either connected to -5V or GND.
> when input = -5V the output should be logic 1 (TTL or CMOS).
> when input = GND the output should be logic 0 (TTL or CMOS).
> The only available voltages that could be used inside A are
> +5V and GND (not -5V).
Simplest is not always best but here is a simple approach: Ground the source of a
J108 (n-channel JFET), tie the drain to +5 through a 1k resistor. The input is
applied to the gate and the output is at the drain. One resistor and one transistor
is pretty simple.
<snip>
>> The input is either connected to -5V or GND.
>> when input = -5V the output should be logic 1 (TTL or CMOS).
>> when input = GND the output should be logic 0 (TTL or CMOS).
>> The only available voltages that could be used inside A are
>> +5V and GND (not -5V).
>Simplest is not always best but here is a simple approach: Ground the source of a
>J108 (n-channel JFET), tie the drain to +5 through a 1k resistor. The input is
>applied to the gate and the output is at the drain. One resistor and one transistor
>is pretty simple.
And since the J108/9/10 can take up to -25V gate-to-drain, it is pretty
robust too. One catch is that the worst-case cut-off voltage for the
J108 is -10V, which makes it difficult to guarantee switching between
0V and -5V on the gate.
The J110, with a worst-case cut-off voltage of -4V, looks more like it.
Bill Sloman (slo…@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
in <5ec94f$…@ratatosk.uio.no>,
: m.k.iranp…@fys.uio.no wrote:
: What is the SIMPLEST way for implementing the box "A" with the
: following specification ?
: The input is either connected to -5V or GND.
: when input = -5V the output should be logic 1 (TTL or CMOS).
: when input = GND the output should be logic 0 (TTL or CMOS).
: The only available voltages that could be used inside A are
: +5V and GND (not -5V).
A MC1489 RS-232 Receiver chip with a 5k ohm resistor between
the threshold adjust for that particular input and the +5 volt
supply. Simple if you need 4 of them at once.
Mark Zenier mzen…@eskimo.com mzen…@netcom.com
Bill Sloman wrote:
> <snip>
> And since the J108/9/10 can take up to -25V gate-to-drain, it is pretty
> robust too. One catch is that the worst-case cut-off voltage for the
> J108 is -10V, which makes it difficult to guarantee switching between
> 0V and -5V on the gate.
> The J110, with a worst-case cut-off voltage of -4V, looks more like it.
True enough! But that spec. is for 1 uA of drain current and I have found that
most J108s are off "enough" with -5 volts for higher current applications like
this. (Actually every J108 I’ve seen would work – I don’t ever get the >400mA
parts.)